Architecture and Process design for the IAL Web Environment |
Current
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Responsible for designing and documenting the network architecture and process for moving Intel Architecture Lab technologies smoothly from the lab, through testing and internal dissemination, and finally (for the lucky few) to the public. Work is in progress.
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Pentium Pro Processor Launch
(Interactive Rendering Machine) |
September 1995 to December 1995
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Archtecture design of a public demonstration of prototype P6 systems using a web-based interface to a pool of machines running raytracing software. Programming, including cgi-bin interface, integration of queueing software, C, Perl, and shell script support. System administration for six prototype machines. Compilation and Makefile
targeted for P6 optimization. Performance tuning (load balancing, distribution, entry gating). Performance monitoring and logging, including remote access via the Web. Supporting documentation and full interface design. One remaining active system is on-line internally at
http://frob.jf.intel.com.
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Design Engineering on P6 IFU |
June 1992-May 1995
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RTL design and preliminary behavioral testing of ITLB.
Complete hierarchical schematic design of iTag, from buses to cache cells. Preliminary floorplanning for iTag.
Complete hierarchical schematic design for ILD, a FUB with greater architectural complexity than many Units. Complete circuit design and simulation for ILD including extensive PLA design, logic optimization, and simulation. Novel approach to fast domino logic (type 1-1/2).
Heavy use of self-timed logic. Massive local bus design and simulation.
Very challenging layout constraints. Layout design effectively communicated, justified, and reused by later proliferations.
Extensive late-stage clock network design, including many shifted, enabled, and shaped clocks. Supervision of a PDS team peaking at six designers. Early attempt to pioneer the use of hypertext-based tools for project documentation.
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Research Engineer for the Electron Beam
Nanolithography Facility at Georgia Tech |
September 1989 to February 1991
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Designed, constructed, and tested hardware interface between an Intel Architecture PC and a Scanning Electron Microscope including control of stage and beam position, as well as beam blanking timing. Positional control was accurate to nanometer scales, timing accurate to fractional microseconds.
Wrote complete GUI-based software package to translate AutoCAD design files into accurately designed beam traces for fabrication of nanometer scaled features on silicon and GaAs HEMT substrates. Software included alignment and exposure controls, as well as monitors for progress.
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