BRIAN W. BRAMLETT
   
   Portland, Oregon / San Francisco, California
   [1]spyke@agora.rdrop.com
   
   _PARTIAL PROJECT LIST_
   Industrial:
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   _Architecture and Process design for the IAL Web Environment_ _Current_
   Responsible for designing and documenting the network architecture and
   process for moving Intel Architecture Lab technologies smoothly from
   the lab, through testing and internal dissemination, and finally (for
   the lucky few) to the public. Work is [2]in progress.
   
   _Pentium Pro Processor Launch
   (Interactive Rendering Machine)_ _September 1995
   to December 1995_
   Archtecture design of a public demonstration of prototype P6 systems
   using a web-based interface to a pool of machines running raytracing
   software. Programming, including cgi-bin interface, integration of
   queueing software, C, Perl, and shell script support. System
   administration for six prototype machines. Compilation and Makefile
   targeted for P6 optimization. Performance tuning (load balancing,
   distribution, entry gating). Performance monitoring and logging,
   including remote access via the Web. Supporting documentation and full
   interface design. One remaining active system is on-line internally at
   [3]http://frob.jf.intel.com.
   
   _Design Engineering on P6 IFU_ _June 1992-May 1995_
   RTL design and preliminary behavioral testing of ITLB.
   
   Complete hierarchical schematic design of iTag, from buses to cache
   cells. Preliminary floorplanning for iTag.
   
   Complete hierarchical schematic design for ILD, a FUB with greater
   architectural complexity than many Units. Complete circuit design and
   simulation for ILD including extensive PLA design, logic optimization,
   and simulation. Novel approach to fast domino logic (type 1-1/2).
   Heavy use of self-timed logic. Massive local bus design and
   simulation. Very challenging layout constraints. Layout design
   effectively communicated, justified, and reused by later
   proliferations. Extensive late-stage clock network design, including
   many shifted, enabled, and shaped clocks. Supervision of a PDS team
   peaking at six designers. Early attempt to pioneer the use of
   hypertext-based tools for project documentation.
   
   _Research Engineer for the Electron Beam
   Nanolithography Facility at Georgia Tech_ _September 1989
   to February 1991_
   Designed, constructed, and tested hardware interface between an Intel
   Architecture PC and a Scanning Electron Microscope including control
   of stage and beam position, as well as beam blanking timing.
   Positional control was accurate to nanometer scales, timing accurate
   to fractional microseconds.
   
   Wrote complete GUI-based software package to translate AutoCAD design
   files into accurately designed beam traces for fabrication of
   nanometer scaled features on silicon and GaAs HEMT substrates.
   Software included alignment and exposure controls, as well as monitors
   for progress.
   
   Academic:
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   _Automatic Algorithmic VLSI_ __
   A set of experimental courses at Georgia Tech to explore techniques
   for designing high-level automated layout tools. Basically a SRTL to
   layout tool for datapath-type (as opposed to DAPR-style "random"
   logic) layout. Projects implemented in C++ including determining
   appropriate data structures, cell scaling, automatic place and route,
   pad ring design. Designed and automatically "taped-out" a simple 8-bit
   RISC microprocessor while working in cooperative teams. (The source of
   the design was a hand-layout from an earlier course--the goal was to
   be able to successfully reproduce the original working part with
   software tools.)
   
   _Advanced Techniques in Rendering_ __
   Explored advanced topics in computer graphics, implementing many as
   evolutions to an initial core rendering program that was written in
   the first few weeks of class.
   
   _Parallel Processing Algorithms and Programming_ __
   Implemented several software studies including thread scheduling based
   on compile-time dependencies, modelled dataflow, systolic, and other
   architectures.
   
   In an independent course, did elementary programming for actual and
   simulated parallel computer architectures.
   
   _Cache Design and Simulation_ __
   Simulated and analysed various cache designs and protocols using real
   program traces, optimizing the design based on simulation results.
   
   Volunteer:
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   _Community Event Calendar_ _Winter-Spring 1996_
   A web-based community event calendar tool that provides a publicly
   administered database of events accessible via web or majordomo.
   Software is being donated to Cascade AIDS Project as a technique to
   bring attention to their web site. Work in progress.
   
   
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   Document URL: http://www.rdrop.com/users/bramlett/projects.html
   ASCII Only: [4]http://www.rdrop.com/users/bramlett/projects.txt
   Last modified: 18 Apr 96