JIM E. NEWTON
SUMMARY:
An experienced problem solver who loves to find elegant solutions to
difficult problems, loves a challenge, and loves to have lots of fun and
experience life.
Ideal Job would Include
Opportunity to advance technically. Lead others to excel. Extensive
travel in Europe and the USA. Opportunity to work with competent,
lively, bright, and communicative people. Ability to practice and
improve spoken foreign language skills. Exhortation to explore life,
the world, culture, and relationships.
EXPERIENCE:
1996 - Present: CADENCE DESIGN SYSTEMS, Munich Germany
Sr. Software Consultant
Promoted to Lead Methodologist
Promoted to Principle Methodologist
Work(ed/ing) with European and Middle Eastern Customers Developing,
Architecting, Improving and Maintaining IC Design Environments.
Accomplishments:
- Managed Software group of 6 Software Engineers. Voted Most
Creative and Innovative by Peers.
- Author of Cadence's Extensible
PCell Methodology (EPM), PCell development system including
PCell Emulator and Stochastic Debugger. EPOS (Extensible PCell
Object System), Additional Layer Concept (ALC), FLEX rules.
- Object Oriented Extensions to the SKILL language including,
CLOS (partial implementation of Common Lisp Object System)
including multiple-dispatch, method combination, application
based (non-class based) dispatch. Exception Handler (VEH)
based on double method dispatch.
- Automated SKILL Source Code Documentation Generator
- CCC Common Centroid device Calculator
- Design Automation: Connectivity Model Manager, Object Oriented
Schematic Check and Save, Virtual Technology Rules (VTR),
Physical Design Quantization PDQ (U.S. Patent).
- Programatic Parameterized Cell Development for CMOS
transistors, contacts, resistors in CMOS technologies and
Archimedian Spiral Inductors for HF technologies, for many
customers and process technologies.
- Technology independent Cadence to Mentor (Ample) design
converter.
- Automated Schematic Library Conversion to convert from
customer proprietary PC base CAD platform to Cadence UNIX
platform.
- Extensive enhancements and to Virtuoso, DLE/VirtuosoXL, Composer layout
and schematic capture environments.
- Automatic (Reticle) Frame Generator, including extensive macro
language for Frame Generator description.
- ECL Topology Analyzer and Level Checker
1992 - 1996: INTEL CORPORATION, Hillsboro OR
Sr. CAD Engineer
Designed and maintained Computer Aided Design (CAD) tools in support of
engineers designing Intel's next generation microprocessor (p6) from
mid-project through tape-out.
Responsibilities include providing Opus user support to team of ~250
engineers, maintaining Composer schematic capture environment, DMS library
maintenance, library corruption detection and repair, providing SKILL
programming support, supervising junior engineer and co-op.
Accomplishments:
- Designed and developed Intel generic property editor, including GUI,
property description data base, consistency checker, and interfaces to
schematic extraction and netlisting.
-
Implemented Intel schematic checks (ISCs) as wrapper around schematic
extraction. The code assures that schematics adhere to Intel schematic
capture rules of connectivity, naming, and labeling.
-
Enhanced library browser to include general purpose copy, move, and
delete functions at cell, cellView, and category levels. GUI includes robust
pattern matching flexibility allowing users to identify target cells.
- Various SKILL programs and GUIs to enhance schematic (Composer)
environment. Including Dynamic Load, Connect By Name, Graphical Data Mapper,
and Hierarchy Descent Engine, as well as SKILL programmers library, including
2D form generator, menu modifier, OS interfaces, math, string, list and
database manipulation functions.
- Inherited, maintained, and enhanced Opus library scanner (dmscan) to
detect and repair library corruptions -- code written in C (ITK), SKILL, and
Perl.
- Developed documentation Hypertext Browser used as project
wide documentation center -- code written in C-shell, Perl, MIF, and HTML.
- Maintained and enhanced intel hierarchical netlister, including
installation, customizing, bug fixes, and providing expert user support.
1988 - 1992: CYPRESS SEMICONDUCTOR, Starkville MS
CAD Engineer
Designed and maintained (CAD) tools in support of engineers designing
integrated circuits. Additional responsibilities included user support,
creating and maintaining various general utility programs, and other system
administration tasks.
Accomplishments:
- Developed and interfaced database management package including daemon
(written in C), applications programs (C and SKILL/lisp) to run and
communicate across SUN network; defined common protocol
- Maintained and enhanced netlisting software, including incorporating
various vendors' simulators (HSPICE, LSIM, MACH-1000, Dracula) into CADENCE
OSS.
- Created a corporate-wide definitive FrameMaker document describing the
usage and graphical aspects of the in-house schematic capture library.
- Rewrote generic SKILL database for integrating vendor CAD system
(CADENCE/EDGE) with in-house element library, reducing possibility of user
error, easing the process of adding library elements, and streamlining code
to approximately 20% of original size.
1985 - 1988: MISSISSIPPI STATE UNIVERSITY
Department of Electrical Engineering, Mississippi State, MS
Undergraduate/Graduate Research Assistant
Computer administration, maintenance and software development in support of
transistor characterization group.
Accomplishments:
- Developed graphics software package to plot experimental data.
- Implemented linear and non-linear circuit simulator.
- Translated software to interface Hewlett-Packard test equipment with
SUN workstation using General Purpose Interface Board (GPIB).
- Implemented partial PostScript interpreter
EDUCATION:
Aug 1992 MA,
Mathematics, Mississippi State University, Mississippi State, MS
Dec 1987 BS,
Electrical Engineering, Mississippi State University, Mississippi
State, MS
PUBLICATIONS:
- U.S. Patent - No. ??????? - PCell Encapsulation
- Extensible PCell Object System: A Multiple-Inheritance approach to
PCell Development. (Proceedings), AIS'04/CAD-2005 An IEEE
sponsored international conference on Artificial Intelligence
Systems and Joint international conference on Intelligent CAD
Systems
- Automated PCell Documentation System International CADENCE
Users Group Conference (Proceedings), Oct 2004.
- Connect By Name Checker,
International CADENCE Users Group Conference (Proceedings), Oct 1994.
- Graphical Data Mapper,
International CADENCE Users Group Conference (Proceedings), Oct 1994.
TECHNICAL SKILLS:
- UNIX (20 years total / 3 years IBM(AIX) / 17 years on SUN /
2 years on VAX-Ultrix) / Linux (4 years)
- CADENCE Design Systems software (Edge and Opus) (16 years)
- Programming languages include:
- Proficiency in
- Common LISP - 2 years
- SKILL (CADENCE version of LISP) (12 years)
- CSH shell (20 years)
- C (10 years) (very rusty)
- Familiarity with
Perl, Python,
HTML, Emacs lisp, PostScript, Bourne Shell,
CVS, Mentor (Ample).
LANGUAGES:
Proficience in English and (spoken) German.
Limited experience in Russian and Italian.
Salary Expectations
100K Euro + Benefits + 6 Weeks or more Vacation Per Year